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products and specifications discussed herein ar e subject to change by micron without notice. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm features pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 1 ?2002 micron technology, inc. all rights reserved. sdram unbuffered dimm (udimm) mt4lsdt464a ? 32mb mt4lsdt864a(i) ? 64mb mt4lsdt1664a(i) ? 128mb for component data sheets, refer to micron?s web site: www.micron.com features ? 168-pin, dual in-line memory module (dimm) ? pc100- and pc133-compliant ? unbuffered ? 32mb (4 meg x 64) 2 , 64mb (8 meg x 64), 128mb (16 meg x 64) ? single +3.3v power supply ? fully synchronous; all signals registered on positive edge of system clock ? internal pipelined operatio n; column address can be changed every clock cycle ? internal sdram banks for hiding row access/ precharge ? programmable burst lengths: 1, 2, 4, 8, or full page ? auto precharge, includes concurrent auto precharge and auto refresh modes ? self refresh mode: 64ms, 4,096-cycle refresh for 32mb and 64mb; 64ms, 8,192-cycle refresh for 128mb ? lvttl-compatible inputs and outputs ? serial presence-detect (spd) ? gold edge contacts figure 1: 168-pin dimm (mo-161) notes: 1. contact micron for product availability. 2. not recommended for new designs. 3. industrial temperature option available in -133 mhz only. options marking ?package ? 168-pin dimm (standard) g ? 168-pin dimm (pb-free) y ? operating temperature range ? commercial (0c to +65c) none ? industrial (?40c to +85c) 1, 3 i ? frequency/cas latency ? 7.5ns (133 mhz)/cl = 2 -13e ? 7.5ns (133 mhz)/cl = 3 -133 ? 8ns (100 mhz)/cl = 2 2 -10e ?pcb ? standard 25.40mm (1.0in) standard 25.4mm (1.0in) table 1: key timing parameters cl = cas (read) latency speed grade industry nomenclature access time setup time hold time cl = 2 cl = 3 -13e pc133 5.4ns ? -13e 133 mhz -133 pc133 ? 5.4ns -133 133 mhz -10e 2 pc100 9ns 7.5ns -10e 100 mhz
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 2 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm features notes: 1. contact micron fo r product availability. 2. not recommended for new designs. 3. the designators for componen t and pcb revision are the last two characters of each part number. consult factory for current revisi on codes. example: mt4lsdt464ag-133g1 table 2: addressing 32mb 64mb 128mb refresh count 4k 4k 8k device banks 4 (ba0, ba1) 4 (ba0, ba1) 4 (ba0, ba1) device configuration 64mb (4 meg x 16) 128mb (8 meg x 16) 256mb (16 meg x 16) row addressing 4k (a0?a11) 4k (a0?a11) 8k (a0?a12) column addressing 256 (a0?a7) 512 (a0?a8) 512 (a0?a8) module ranks 1 (s0#, s2#) 1 (s0#, s2#) 1 (s0#, s2#) table 3: part numbers and timing parameters part number 3 module density configuration system bus speed mt4lsdt464ag-13e_ 1 32mb 4 meg x 64 133 mhz mt4lsdt464ay-13e_ 2 32mb 4 meg x 64 133 mhz mt4lsdt464ag-133_ 2 32mb 4 meg x 64 133 mhz mt4lsdt464ay-133_ 2 32mb 4 meg x 64 133 mhz mt4lsdt464ag-10e_ 2 32mb 4 meg x 64 100 mhz MT4LSDT464AY-10E_ 1 32mb 4 meg x 64 100 mhz mt4lsdt864ag-13e_ 1 64mb 8 meg x 64 133 mhz mt4lsdt864ay-13e_ 64mb 8 meg x 64 133 mhz mt4lsdt864aig-133_ 1 64mb 8 meg x 64 133 mhz mt4lsdt864ag-133_ 1 64mb 8 meg x 64 133 mhz mt4lsdt864aiy-133_ 1 64mb 8 meg x 64 133 mhz mt4lsdt864ay-133_ 64mb 8 meg x 64 133 mhz mt4lsdt864ag-10e_ 2 64mb 8 meg x 64 100 mhz mt4lsdt864ay-10e_ 1 64mb 8 meg x 64 100 mhz mt4lsdt1664ag-13e_ 128mb 16 meg x 64 133 mhz mt4lsdt1664ay-13e_ 128mb 16 meg x 64 133 mhz mt4lsdt1664a i g-133_ 1 128mb 16 meg x 64 133 mhz mt4lsdt1664ag-133_ 128mb 16 meg x 64 133 mhz mt4lsdt1664a i y-133_ 1 128mb 16 meg x 64 133 mhz mt4lsdt1664ay-133_ 128mb 16 meg x 64 133 mhz mt4lsdt1664ag-10e_ 2 128mb 16 meg x 64 100 mhz mt4lsdt1664ay-10e_ 2 128mb 16 meg x 64 100 mhz
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 3 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm pin assignments and descriptions pin assignments and descriptions notes: 1. pin 126 is nc for 32mb and 64mb modules, or a12 for the 128mb module. figure 2: pin locations (168-pin dimm) table 4: pin assignments 168-pin dimm front 168-pin dimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1v ss 22 dnu 43 v ss 64 v ss 85 v ss 106 dnu 127 v ss 148 v ss 2dq023 v ss 44 nc 65 dq21 86 dq32 107 v ss 128 cke0 149 dq53 3 dq1 24 nc 45 s2# 66 dq22 87 dq33 108 nc 129 dnu 150 dq54 4 dq2 25 nc 46 dqm2 67 dq23 88 dq34 109 nc 130 dqm6 151 dq55 5dq326v dd 47 dqm3 68 v ss 89 dq35 110 v dd 131 dqm7 152 v ss 6v dd 27 we# 48 nc 69 dq24 90 v dd 111 cas# 132 dnu 153 dq56 7 dq4 28 dqm0 49 v dd 70 dq25 91 dq36 112 dqm4 133 v dd 154 dq57 8 dq5 29 dqm1 50 nc 71 dq26 92 dq37 113 dqm5 134 nc 155 dq58 9 dq6 30 s0# 51 nc 72 dq27 93 dq38 114 dnu 135 nc 156 dq59 10 dq7 31 nc 52 dnu 73 v dd 94 dq39 115 ras# 136 dnu 157 v dd 11 dq8 32 v ss 53 dnu 74 dq28 95 dq40 116 v ss 137 dnu 158 dq60 12 v ss 33 a0 54 v ss 75 dq29 96 v ss 117 a1 138 v ss 159 dq61 13 dq9 34 a2 55 dq16 76 dq30 97 dq41 118 a3 139 dq48 160 dq62 14 dq10 35 a4 56 dq17 77 dq31 98 dq42 119 a5 140 dq49 161 dq63 15 dq11 36 a6 57 dq18 78 v ss 99 dq43 120 a7 141 dq50 162 v ss 16 dq12 37 a8 58 dq19 79 ck2 100 dq44 121 a9 142 dq51 163 dnu 17 dq13 38 a10 59 v dd 80 nc 101 dq45 122 ba0 143 v dd 164 nc 18 v dd 39 ba1 60 dq20 81 nc 102 v dd 123 a11 144 dq52 165 sa0 19 dq14 40 v dd 61 nc 82 sda 103 dq46 124 v dd 145 nc 166 sa1 20 dq15 41 v dd 62 nc 83 scl 104 dq47 125 dnu 146 nc 167 sa2 21 dnu 42 ck0 63 nc 84 v dd 105 dnu 126 nc/a12 1 147 nc 168 v dd u1 u2 u4 u5 u6 no components on this side of module front view back view pin 1 pin 84 pin 85 pin 168
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 4 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm pin assignments and descriptions table 5: pin descriptions pins may not correlate with symbols; refer to table 4 on page 3 for more information pin numbers symbol type description 27, 111, 115 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. 42, 79 ck0, ck2 input clock: ck is driven by the system clock. all sdram input signals are sampled on the posi tive edge of ck. ck also increments the internal burst co unter and controls the output registers. 128 cke0 input clock enable: cke activates (high) and deactivates (low) the ck signal. deactivating the clock provides precharge power-down and self refresh operation (all device banks idle) or clock suspend operation (burst access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchronous until after exiting the same mode . the input buffers, including ck, are disabled during power- down and self refresh modes, providing low standby power. 30, 45 s0#, s2# input chip select: s# enables (registered low) and disables (registered high) the command decoder. all commands are masked when s# is registered high. s# is considered part of the command code. 28, 29, 46, 47, 112, 113, 130, 131 dqmb0? dqmb7 input input/output mask: dqmb is an input ma sk signal for write accesses and an output enable signal for read accesses. input data is masked when dqmb is sampled high during a write cycle. the output buffers are pl aced in a high-z state (two- clock latency) when dqmb is sampled high during a read cycle. 39, 122 ba0, ba1 input bank address: ba0 and ba1 define to which device bank the active, read, write, or pr echarge command is being applied. 33?38, 117?121, 123, 126 (128mb) a0?a11 (32mb, 64mb) a0?a12 (128mb) input address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective device bank. a10 sampled during a precharge co mmand determines whether the precharge applies to one device bank (a10 low, device bank selected by ba0, ba1) or all device banks (a10 high). the address inputs also provid e the op-code during a mode register set command. 83 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data tran sfer to and from the module. 165?167 sa0?sa2 input presence-detect address inputs: these pins are used to configure the presence-detect device. 82 sda input/output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence- detect portion of the module. 2?5, 7?11, 13?17, 19?20, 55?58, 60, 65?67, 69?72, 74?77, 86?89, 91?95, 97?101, 103?104, 139? 142, 144, 149?151, 153? 156, 158?161 dq0?dq63 in put/output data i/os: data bus.
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 5 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm pin assignments and descriptions 6, 18, 26, 40, 41, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 v dd supply power supply: +3.3v 0.3v. 1, 12, 23, 32, 43, 54, 64, 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 v ss supply ground. 21, 22, 52, 53, 105, 106, 114, 125, 129, 132, 163 dnu ? do not use: these pins are not used on these modules, but are assigned pins on other mo dules in this product family. 24, 25, 31, 44, 48, 50, 51, 61, 62, 63, 80, 81, 108, 109, 126 (32mb, 64mb), 134, 135, 145?147, 164 nc ? not connected: these pins are not connected on these modules. table 5: pin descriptions (continued) pins may not correlate with symbols; refer to table 4 on page 3 for more information pin numbers symbol type description
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 6 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm functional block diagram functional block diagram figure 3: functional block diagram notes: 1. all resistor values are 10 unless otherwise specified. 2. per industry standard, micron modules use va rious component speed gr ades as referenced in the module part numbering guide found on micron?s web site: www.micron.com/support . 3. standard modules use the following sdram devices: mt48lc4m16a2tg(it) (32mb); mt48lc8m16a2tg(it) (64mb); mt48lc16m16a2tg(it) (128mb). 4. pb-free modules use the following sdra m devices: mt48lc4m16a2p(it) (32mb); mt48lc8m16a2p(it) (64mb); mt48lc16m16a2p(it) (128mb). dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 dqmh u1 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqmb4 s2# ras# cas# cke0 we# ras#: sdrams cas#: sdrams cke: sdrams we#: sdrams a0?a11: sdrams a0?a12: sdrams ba0?ba1: sdrams a0?a11 (32mb/64mb) a0?a12 (128mb) ba0?ba1 v dd v ss sdrams sdrams dq dq dq dq dq dq dq dq dqml cs# dqmb0 dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 dqmh u2 dq dq dq dq dq dq dq dq dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqmb5 dq dq dq dq dq dq dq dq dqml cs# dqmb1 dq23 dq22 dq21 dq20 dq19 dq18 dq17 dq16 dqmh u4 dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqmb6 dq dq dq dq dq dq dq dq dqml cs# dqmb2 dq31 dq30 dq29 dq28 dq27 dq26 dq25 dq24 dqmh u5 dq dq dq dq dq dq dq dq dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqmb7 dq dq dq dq dq dq dq dq dqml cs# dqm3 s0# 10pf ck1, ck3 ck0 11.2pf a0 sa0 spd eeprom u6 sda a1 sa1 a2 sa2 wp scl u1 u2 ck2 13.6pf u4 u5
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 7 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm general description general description the micron mt4lsdt464a, mt4lsdt864a(i), and mt4lsdt1664a(i) are high-speed cmos, dynamic random access, 32mb, 64mb, and 128mb memory modules organized in a x64 configuration. these modules use sdram devices which are internally config- ured as quad-bank drams with a synchronous interface (all signals are registered on the positive edge of the clock signals ck). read and write accesses to the sdram modu le are burst oriented; accesses start at a selected location and continue for a prog rammed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the devi ce bank and row to be accessed (ba0, ba1 select the device bank, a0?a11 for 32mb an d 64mb; a0?a12 for 128mb select the device row). the address bits registered coincident with the read or write command (a0?a7 for 32mb; a0?a8 for 64mb and 128mb) are used to select the starting device column location for the burst access. these modules provide for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or the full page with a burst te rminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. these modules use an internal pipelined architecture to achieve high- speed operation. this architecture is compatible with the 2 n rule of prefetch architec- tures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one device bank while accessing one of the other three device banks will hide th e precharge cycles and provide seamless, high-speed, random access operation. these modules are designed to operate in 3.3v, low-power memory systems. an auto refresh mode is provided, along with a po wer-saving, power-down mode. all inputs, outputs, and clocks are lvttl-compatible. sdram modules offer substantial advances in dram operating performance, including the ability to synchronously burst data at a high data rate with automatic column- address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. for more inform ation regarding sdram operation, refer to the 64mb, 128mb, or 256mb sdram component data sheets. serial presence-detect operation these modules incorporate serial presence-d etect (spd). the spd function is imple- mented using a 2,048-bit eeprom. this nonvol atile storage de vice contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) an d the slave eeprom device (di mm) occur via a standard iic bus using the dimm?s scl (clock) and sda (data) signals. write protect (wp) is tied to ground on the module, permanently disabling hardware write protect. initialization sdrams must be powered up and initiali zed in a predefined manner. operational procedures other than those specified may resu lt in undefined operation. once power is applied to v dd and v dd q (simultaneously) and the cloc k is stable (stable clock is
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 8 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm mode register definition defined as a signal cycling wi thin timing constraints specified for the clock pin), the sdram requires a 100s delay prior to is suing any command other than a command inhibit or nop. starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or nop commands should be applied. once the 100s delay has been satisfied wi th at least one command inhibit or nop command having been applied, a precharge command should be applied. all device banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. mode register definition the mode register is used to define the spec ific mode of operation of the sdram. this definition includes the selection of a burst length, a burst type, a cas latency, an oper- ating mode, and a write burst mode, as shown in figure 4 on page 10. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0?m2 specify the burs t length, m3 specifies the type of burst (sequential or interleaved), m4?m6 specify th e cas latency, m7 and m8 specify the oper- ating mode, m9 specifies the write burst mode, and m10 and m11 are reserved for future use. for the 128mb module, address a12 (m12) is undefined but should be driven low during loading of the mode register. the mode register must be loaded when all device banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements will resu lt in unspecified operation. burst length (bl) read and write accesses to the sdram are bu rst oriented, with th e burst length being programmable, as shown in figure 4 on page 10. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4, or 8 locati ons are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses fo r that burst take place within this block, meaning that the burst will wrap within the bl ock if a boundary is reached, as shown in table 6 on page 11. the block is uniquely selected by a1?a i when bl = 2, a2?a i when bl = 4, and a3?a i when bl = 8. see note 8 of table 6 on page 11 for a i values. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached, as shown in table 6 on page 11.
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 9 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm mode register definition burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is de termined by the burst length, the burst type, and the starting column address, as shown in table 6 on page 11.
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 10 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm mode register definition figure 4: mode register definition diagram notes: 1. m11 and m10 should be programmed = ?0, 0? to ensure compatibility with future devices. 2. m12, m11, and m10 should be programmed = ?0, 0, 0? to ensure comp atibility with future devices. 128mb module m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 ? 0 ? defined ? 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6?m0 m8 m7 op mode a10 a11 10 11 reserved 2 wb 0 1 write burst mode programmed bl single location access m9 a12 12 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 op mode a10 a11 10 11 reserved 1 wb 32mb and 64mb modules
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 11 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm mode register definition notes: 1. for full-page accesses: y = 256 (32mb); y = 512 (64mb/128mb). 2. for bl = 2, a1?a i select the block-of-two burst; a0 se lects the starting column within the block. 3. for bl = 4, a2?a i select the block-of-four burst; a0?a1 se lect the starting column within the block. 4. for bl = 8, a3?a i select the block-of-eight burst; a0?a 2 select the starting column within the block. 5. for a full-page burst, the fu ll row is selected and a0?a i select the sta rting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for bl = 1, a0?a i select the unique column to be ac cessed, and mode register bit m3 is ignored. 8. i = 7 for 32mb; i = 8 for 64mb and 128mb. table 6: burst definition table burst length starting column address order of accesses within a burst type = sequential type = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-4-5-6-7-0-1-2 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = a0?a i (location 0? y) cn, cn + 1, cn + 2, cn + 3, cn + 4. . . cn - 1, cn . . . not supported
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 12 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm mode register definition figure 5: cas latency diagram cas latency (cl) cl is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dq will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the re levant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in figure 5. table 7 on page 13 indicates the operating frequencies at which each cl setting can be used. reserved states should not be used becaus e unknown operation or incompatibility with future versions may result. operating mode the normal operating mode is selected by se tting m7 and m8 to zero; the other combi- nations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the bl programmed via m0?m2 a pplies to both read and write bursts; when m9 = 1, the programmed bl applies to read bursts, but write accesses are single- location (nonburst) accesses. clk dq t2 t1 t3 t0 cl = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t 2 t1 t 3 t 0 cl = 2 lz d out t oh t command nop read t ac nop
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 13 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm mode register definition table 7: cas latency table speed allowable operating clock frequency (mhz) cl = 2 cl = 3 -13e 133 143 -133 100 133 -10e 100 n/a
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 14 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm commands commands this truth table provides a general reference of available commands. for a more detailed description of commands and operations, refer to the 64mb, 128mb, or 256mb sdram component data sheet. notes: 1. a0?a11 define the op-code written to the mode register, and for the 128mb module, a12 should be driven low. 2. a0?a11 (32mb and 64mb) or a0?a12 (128mb) provide device row address, and ba0, ba1 determine which device bank is made active. 3. a0?a7 (32mb) or a0?a8 (64mb and 128mb) provide device column address; a10 high enables the auto precharge f eature (nonpersistent) while a10 low disables the auto pre- charge feature; ba0, ba1 determine which devi ce bank is being read from or written to. 4. a10 low: ba0, ba1 determine the device ba nk being precharged. a10 high: all device banks precharged and ba0, ba1 are ?don?t care.? 5. this command is auto refresh if cke is high, self refresh if cke is low. 6. internal refresh counter controls device row ad dressing; all inputs and i/os are ?don?t care? except for cke. 7. activates or deactivates the dq during writes (zero-clock delay) and reads (two-clock delay). table 8: truth table ? commands and dqmb operation notes appear below; cke is high for all commands shown except self refresh name (function) cs# ras# cas# we# dqmb address dqs notes command inhibit (nop) hxxx x x x no operation (nop) lhhh x x x active (select bank and activate row) l l h h x bank/row x 1 read (select bank and column, and start read burst) lhlhl/h 7 bank/col x 3 write (select bank and column, and start write burst) l h l l l/h 7 bank/col valid 3 burst terminate lhhl x x active precharge (deactivate row in bank or banks) llhl x code x 4 auto refresh or self refresh (enter self refresh mode) lllh x x x 5, 6 load mode register llll xop-code x 1 write enable/output enable ???? l ? active 7 write inhibit/output high-z ???? h ? high-z 7
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 15 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm electrical specifications electrical specifications stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reli- ability. absolute maximum ratings capacitance timing and oper ating conditions table 9: absolute maximum ratings parameter symbol min max units voltage on v dd , v dd q supply relative to v ss ?1.0 +4.6 v voltage on inputs, nc or i/o pins relative to v ss ?1.0 +4.6 v operating temperature t opr (commercial - ambient) 0+65c operating temperature t opr (industrial - ambient) ?40 +85 c storage temperature (plastic) ?55 +150 c table 10: capacitance notes 1, 2; notes appear on page 20 parameter symbol min max units input capacitance: address and command c i 1 10 15.2 pf input capacitance: s# c i 2 57.6pf input capacitance: ck0 c i 3 a 16.2 18.2 pf input capacitance: ck2 c i 3 b 18.6 20.6 pf input capacitance: dqmb c i 4 2.5 3.8 pf input/output capacitance: dq c io 46pf table 11: ac functional characteristics notes: 5, 6, 8, 9, 11, 31; notes appear on page 20 parameter symbol -13e -133 -10e units notes read/write command to read/write command t ccd 1 1 1 t ck 17 cke to clock disable or power-down entry mode t cked 1 1 1 t ck 14 cke to clock enable or power-down exit setup mode t ped 1 1 1 t ck 14 dqm to input data delay t dqd 0 0 0 t ck 17 dqm to data mask during writes t dqm 0 0 0 t ck 17 dqm to data high-impedance during reads t dqz 2 2 2 t ck 17 write command to input data delay t dwd 0 0 0 t ck 17 data-in to active command t dal 4 5 4 t ck 15, 21 data-in to precharge command t dpl 2 2 2 t ck 16, 21 last data-in to burst stop command t bdl 1 1 1 t ck 17 last data-in to ne w read/write command t cdl 1 1 1 t ck 17 last data-in to precharge command t rdl 2 2 2 t ck 16, 21 load mode register command to active or refresh command t mrd 2 2 2 t ck 26
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 16 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm electrical specifications data-out to high-imp edance from precharge command cl = 3 t roh(3) 3 3 3 t ck 17 cl = 2 t roh(2) 2 2 2 t ck 17 table 12: electrical characteristics and recommended ac operating conditions notes: 5, 6, 8, 9, 11, 31; notes appear on page 20; v dd , v dd q = +3.3v 0.3v ac characteristics -13e -133 -10e units notes parameter symbol min max min max min max access time from clk (positive edge) cl = 3 t ac(3) ? 5.4 ? 5.4 ? ? ns 27 cl = 2 t ac(2) ? 5.4 ? 6 ? 6 ns address hold time t ah 0.8 ? 0.8 ? 1 ? ns address setup time t as 1.5 ? 1.5 ? 2 ? ns clk high-level width t ch 2.5 ? 2.5 ? 3 ? ns clk low-level width t cl 2.5 ? 2.5 ? 3 ? ns clock cycle time cl = 3 t ck(3) 7 ? 7.5 ? 8 ? ns 23 cl = 2 t ck(2) 7.5 ? 10 ? 10 ? ns 23 cke hold time t ckh 0.8 ? 0.8 ? 1 ? ns cke setup time t cks 1.5 ? 1.5 ? 2 ? ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 ? 0.8 ? 1 ? ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 ? 1.5 ? 2 ? ns data-in hold time t dh 0.8 ? 0.8 ? 1 ? ns data-in setup time t ds 1.5 ? 1.5 ? 2 ? ns data-out high-impedance time cl = 3 t hz(3) ? 5.4 ? 5.4 ? 6 ns 10 cl = 2 t hz(2) ? 5.4 ? 6 ? 6 ns 10 data-out low-impedance time t lz 1 ? 1 ? 1 ? ns data-out hold time (load) t oh 3 ? 3 ? 3 ? ns data-out hold time (no load) t oh n 1.8 ? 1.8 ? 1.8 ? ns 28 active to precharge command t ras 37 120,000 44 120,000 50 120,000 ns 32 active to active command period t rc 60 ? 66 ? 70 ? ns active to read or write delay t rcd 15 ? 20 ? 20 ? ns refresh period (8,192 rows) t ref ? 64 ? 64 ? 64 ms auto refresh period t rfc 66 ? 66 ? 70 ? ns precharge command period t rp 15 ? 20 ? 20 ? ns active bank a to active bank b command t rrd 14 ? 15 ? 20 ? ns transition time t t 0.3 1.2 0.3 1.2 0.3 1.2 ns 7 write recovery time t wr 1 clk + 7ns ?1 clk + 7.5ns ?1 clk + 7ns ?ns24 14 ? 15 ? 15 ? ns 25 exit self refresh to active command t xsr 67 ? 75 ? 80 ? ns 20 table 11: ac functional characteristics (continued) notes: 5, 6, 8, 9, 11, 31; notes appear on page 20 parameter symbol -13e -133 -10e units notes
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 17 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm electrical specifications table 13: dc electrical characteristics and operating conditions notes: 1, 5, 6; note s appear on page 20; v dd , v dd q = +3.3v 0.3v parameter/condition symbol min max units notes supply voltage v dd , v dd q3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v22 input low voltage: logic 0; all inputs v il ?0.3 0.8 v 22 input leakage current: any input 0v v in v dd (all other pins not under test = 0v) i i ?20 20 a 33 ?10 10 ?5 5 output leakage current: dqs are disabled; 0v v out v dd q i oz ?5 5 a 33 output levels: output high voltage (i out = ?4ma) v oh 2.4 ? v output low voltage: (i out = 4ma) v ol ?0.4v
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 18 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm electrical specifications i dd specifications table 14: i dd specifications an d conditions ? 32mb notes: 1, 5, 6, 11, 13; notes appear on page 20; v dd , v dd q = +3.3v 0.3v; dram components only parameter/condition symbol max units notes -13e -133 -10e operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 500 460 380 ma 3, 18, 19, 29 standby current: power-down mode; all device banks idle; cke = low i dd 2 888 ma 29 standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 180 180 140 ma 3, 12, 19, 29 operating current: burst mode; continuous burst; read or write; all devi ce banks active i dd 4 600 560 480 ma 3, 18, 19, 29 auto refresh current: cs# = high; cke = high t rfc = t rfc (min) i dd 5 920 840 760 ma 3, 12, 18, 19, 29, 30 t rfc = 15.62s i dd 6 12 12 12 ma self refresh current: cke 0.2v i dd 7 444 ma 4 table 15: i dd specifications an d conditions ? 64mb notes: 1, 5, 6, 11, 13; notes appear on page 20; v dd , v dd q = +3.3v 0.3v; dram components only parameter/condition symbol max units notes -13e -133 -10e operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 640 600 560 ma 3, 18, 19, 29 standby current: power-down mode; all device banks idle; cke = low i dd 2 888 ma 29 standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 200 200 160 ma 3, 12, 19, 29 operating current: burst mode; continuous burst; read or write; all devi ce banks active i dd 4 660 600 560 ma 3, 18, 19, 29 auto refresh current: cs# = high; cke = high t rfc = t rfc (min) i dd 5 1,320 1,240 1,080 ma 3, 12, 18, 19, 29, 30 t rfc = 15.62s i dd 6 12 12 12 ma self refresh current: cke 0.2v i dd 7 888 ma 4 table 16: i dd specifications and conditions ? 128mb notes: 1, 5, 6, 11, 13; notes appear on page 20; v dd , v dd q = +3.3v 0.3v; dram components only parameter/condition symbol max units notes -13e -133 -10e operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 540 500 500 ma 3, 18, 19, 29 standby current: power-down mode; all device banks idle; cke = low i dd 2 888 ma 29 standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 160 160 160 ma 3, 12, 19, 29 operating current: burst mode; continuous burst; read or write; all devi ce banks active i dd 4 540 540 540 ma 3, 18, 19, 29
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 19 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm electrical specifications auto refresh current: cs# = high; cke = high t rfc = t rfc (min) i dd 5 1,140 1,080 1,080 ma 3, 12, 18, 19, 29, 30 t rfc = 7.81s i dd 6 14 14 14 ma self refresh current: cke 0.2v i dd 7 10 10 10 ma 4 table 16: i dd specifications and conditions ? 128mb (continued) notes: 1, 5, 6, 11, 13; notes appear on page 20; v dd , v dd q = +3.3v 0.3v; dram components only parameter/condition symbol max units notes -13e -133 -10e
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 20 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm notes notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd , v dd q = +3.3v; f = 1 mhz; t a = 25c; pin under test biased at 1.4v. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured (0c t a +70c for commercial, ? 40c t a +85c for industrial). 6. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be pow- ered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups shou ld be repeated anytime the t ref refresh require- ment is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specification, the cl ock and cke must tran- sit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured at 1.5 v with equivalent load: 10. t hz defines the time at which the output achi eves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1ns, then the timing is ref- erenced at v il (max) and v ih (min) and no longer at the isv crossover point. 12. other input signals are allowed to transiti on no more than once every two clocks and are otherwise at valid v ih or v il levels. 13. i dd specifications are tested after th e device is properly initialized. 14. timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 18. the i dd current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. address transitions average on e transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 10ns for -10e; t ck = 7.5ns for -133 and -13e. 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one-third of the cycle rate. v il undershoot: v il (min) = ? 2v for a pulse width 3ns. q 50pf
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 21 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm notes 23. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for th e clock pin) during access or precharge states (read, write, including t wr and precharge comman ds). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge timing budget ( t rp) begins 7ns for -13e; 7.5ns for -133; and 7ns for -10e after the firs t clock delay, after the last write is exe- cuted. may not exceed limit set for precharge mode. 25. precharge mode only. 26. jedec and pc100 specify three clocks. 27. t ac for -133/-13e at cl = 3 with no load is 4.6ns and is guaranteed by design. 28. parameter guaranteed by design. 29. for -13e, cl = 2 and t ck = 7.5ns; for -133, cl = 3 and t ck = 7.5ns; for -10e, cl = 2 and t ck = 10ns. 30. cke is high during refresh command period t rfc (min), else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 31. refer to device data sheet for timing waveforms. 32. the value of t ras used in -13e speed grade modules is calculated from t rc - t rp. 33. leakage number reflects the worst-case leakage possible through the module pin, not what each memory device contributes.
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 22 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm serial presence-detect serial presence-detect spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions, as indicated in figure 6 on page 22 and figure 7 on page 23. spd start condition all commands are preceded by the start cond ition, which is a hi gh-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not re spond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condition, which is a low-to-high tran- sition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data, as indicated in figure 8 on page 23. the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both th e device and a write operation have been selected, the spd device will respond with an acknowledge after the receipt of each subsequent eight-bit word. in the read mode, the spd device will transmit eight bits of data, release the sda line, and monitor the line for an acknowledge. if an acknowledge is detected and no stop conditio n is generated by the master, the slave will continue to transmit data. if an acknowledge is not dete cted, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. figure 6: data validity scl sda data stable data stable data change
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 23 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm serial presence-detect figure 7: definition of start and stop figure 8: acknowledge response from receiver table 17: eeprom device select code the most significant bit (b7) is sent first device type identifier chip enable rw# b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1 0 1 0 sa2 sa1 sa0 rw# protection register select code 0 1 1 0 sa2 sa1 sa0 rw# table 18: eeprom operating modes mode rw# bit w#c bytes initial sequence current address read 1v ih or v il 1 start, device select, rw# = ?1? random address read 0v ih or v il 1 start, device select, rw# = ?0?, address 1v ih or v il 1 restart, device select, rw# = ?1? sequential read 1v ih or v il 1 similar to current or random address read byte write 0v il 1 start, device select, rw# = ?0? page write 0v il 16 start, device select, rw# = ?0? scl sda start bit stop bit scl from master data output from transmitter data output from receiver 9 8 acknowledge
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 24 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm serial presence-detect figure 9: spd eeprom timing diagram table 19: serial presence-detec t eeprom dc operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units supply voltage v dd 33.6v input high voltage: logic 1; all inputs v ih v dd x 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il ?1 v dd x 0.3 v output low voltage: i outl = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li ?10a output leakage current: v out = gnd to v dd i lo ?10a standby current: scl = sda = v dd - 0.3v; all other inputs = gnd or 3.3v 10% i sb ?30a power supply current: scl clock frequency = 100 khz i dd ?2ma table 20: serial presence-detec t eeprom ac operating conditions notes appear below; all vo ltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 ? s data-out hold time t dh 200 ? ns sda and scl fall time t f?300ns2 data-in hold time t hd:dat 0 ? s start condition hold time t hd:sta 0.6 ? s clock high period t high 0.6 ? s noise suppression time con stant at scl, sda inputs t i?50ns clock low period t low 1.3 ? s sda and scl rise time t r?0.3s2 scl clock frequency f scl ? 400 khz data-in setup time t su:dat 100 ? ns start condition setup time t su:sta 0.6 ? s 3 stop condition setup time t su:sto 0.6 ? s scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 25 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm serial presence-detect notes: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition, or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a vali d stop condition of a write sequence to the end of the eeprom internal erase/program cycle. du ring the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to pull-up resistor, and the eeprom does not respond to its slave address. write cycle time t wrc ? 10 ms 4 table 20: serial presence-detect eepro m ac operating conditions (continued) notes appear below; all vo ltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units notes
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 26 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm serial presence-detect table 21: serial presence-detect matrix ?1?/?0?: serial data , ?driven to high?/?driven to low.? byte description entry (version) 32mb 64mb 128mb 0 number of bytes used by micron 128 808080 1 total number of spd memory bytes 256 080808 2 memory type sdram 040404 3 number of row addresses 12 or 13 0c 0c 0d 4 number of column addresses 8 or 9 080909 5 number of banks 1 010101 6 module data width 64 40 40 40 7 module data width (continued) 0 000000 8 module voltage interface levels lvttl 010101 9 sdram cycle time, t ck (cl = 3) 7ns (-13e) 7.5ns (-133) 8ns (-10e) 70 75 80 70 75 80 70 75 80 10 sdram access from clock, t ac (cl = 3) 5.4ns (-13e/-133) 6ns (-10e) 54 60 54 60 54 60 11 module configuration type none 00 00 00 12 refresh rate/type (80) 15.6s/self (82) 7.81s/self 80 80 82 13 sdram width (primary sdram) 16 10 10 10 14 error-checking sdram data width none 00 00 00 15 minimum clock delay, t ccd 1 010101 16 burst lengths supported 1, 2, 4, 8, page 8f 8f 8f 17 number of internal banks on sdram device 4 040404 18 cas latencies supported 2, 3 060606 19 cs latency 0 010101 20 we latency 0 010101 21 sdram module attributes unbuffered 00 00 00 22 sdram device attributes: general 0e 0e 0e 0e 23 sdram cycle time, t ck (cl = 2) 7.5ns (-13e) 10ns (-133/-10e) 75 a0 75 a0 75 a0 24 sdram access from ck, t ac (cl = 2) 5.4ns (-13e) 6ns (-133/-10e) 54 60 54 60 54 60 25 sdram cycle time, t ck (cl = 1) ? 000000 26 sdram access from ck, t ac (cl = 1) ? 000000 27 minimum row precharge time, t rp 15ns (-13e) 20ns (-133/-10e) 0f 14 0f 14 0f 14 28 minimum row active to row active, t rrd 14ns (-13e) 15ns (-133) 20ns (-10e) 0e 0f 14 0e 0f 14 0e 0f 14 29 minimum ras# to cas# delay, t rcd 15ns (-13e) 20ns (-133/-10e) 0f 14 0f 14 0f 14 30 minimum ras# pulse width, t ras (see note 1) 45ns (-13e) 44ns (-133) 50ns (-10e) 2d 2c 32 2d 2c 32 2d 2c 32 31 module rank density 32mb, 64mb, or 128mb 08 10 20 32 command and address setup time 1.5ns (-13e/-133) 2ns (-10e) 15 20 15 20 15 20
pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 27 ?2002 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm serial presence-detect notes: 1. the value of t ras used for the -13e pa rt is calculated from t rc - t rp. actual device specifica- tion value is 37ns. 33 command and address hold time 0.8ns (-13e/-133) 1ns (-10e) 08 10 08 10 08 10 34 data signal in put setup time 1.5ns (-13e/-133) 2ns (-10e) 15 20 15 20 15 20 35 data signal in put hold time 0.8ns (-13e/-133) 1ns (-10e) 08 10 08 10 08 10 36?61 reserved 00 00 00 41 device minimum active/auto-refresh time, t rc 60ns (-13e) 66ns (-133) 70ns (10e) 3c 42 46 3c 42 46 3c 42 46 42?61 reserved 00 00 00 62 spd revision 2 020202 63 checksum for bytes 0?62 -13e -133 -10e 82 ce 1a 8b d7 23 9e ea 36 64 manufacturer?s jedec id code micron 2c 2c 2c 65?71 manufacturer?s jedec id code (continued) ff ff ff 72 manufacturing location 1?12 01?0c 01?0c 01?0c 73?90 module part number (ascii) variable data variable data variable data 91 pcb identification code 1?9 01?09 01?09 01?09 92 identification co de (continued) 0 000000 93 year of manufacture in bcd variable data variable data variable data 94 week of manufacture in bcd variable data variable data variable data 95?98 module serial number variable data variable data variable data 99?125 manufacturer-specifi c data (reserved) variable data variable data variable data 126 system frequency 100/133 mhz 64 64 64 127 sdram component and clock detail af af af table 21: serial presence-detect matrix (continued) ?1?/?0?: serial data , ?driven to high?/?driven to low.? byte description entry (version) 32mb 64mb 128mb
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. althou gh considered final, these specifications are subject to change, as further product development and data characte rization sometimes occur. 32mb, 64mb, 128mb (x64, sr) 168-pin sdram udimm module dimensions pdf: 09005aef8078bc7c/source: 09005aef8078bcd3 micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64ag.fm - rev. d 1/07 en 28 ?2002 micron technology, inc. all rights reserved. module dimensions figure 10: 168-pin dimm notes: 1. all dimensions in millimeters (inc hes); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference on ly. refer to the jedec mo document for com- plete design dimensions. pin 1 (pin 85 on backside) 17.78 (0.700) typ 3.00 (0.118) (2x) 3.00 (0.118) typ 115.57 (4.550) 1.27 (0.050) typ 3.00 (0.118) typ 1.00 (0.039) typ 2.00 (0.079) r (2x) 1.00 (0.039) r (2x) front view 3.25 (0.128) 3.00 (0.118) pin 84 (pin 168 on backside) (2x) 6.35 (0.250) typ 42.18 (1.661) 66.68 (2.625) 25.53 (1.005) 25.27 (0.995) 133.05 (5.256) 133.20 (5.244) 3.18 (0.125) max 1.37 (0.054) 1.17 (0.046) u1 u2 u4 u5 u6

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